1. Field of the Invention
The embodiments disclosed herein relate to the static noise margin (SNM) of static random access memory (SRAM) cells in an SRAM array and, more specifically, to a circuit and method for repeatedly monitoring the SNM of SRAM cells in an SRAM array
2. Description of the Related Art
Those skilled in the art will recognize that size and power scaling are key factors considered in modern integrated circuit design. One common technique for power scaling is to reduce the power supply voltage. However, reducing the power supply voltage to a static random access memory (SRAM) cell can cause the SRAM cell to be more susceptible to stability failures (i.e., memory fails). Specifically, reducing the power supply voltage to an SRAM cell below a certain minimum voltage level will reduce the SRAM cell's static noise margin (SNM). The SNM refers to the amount of external DC voltage noise required to change the state of the SRAM cell. Thus, when the SNM is reduced, so is the amount of voltage noise required for data stored in the SRAM cell to be lost. Furthermore, the SNM of an SRAM cell will degrade (i.e., will be reduced) over time due to various aging mechanisms, also referred to as performance degradation mechanisms associated with the various transistors within the SRAM cell. Such aging mechanisms include, but are not limited to, gate oxide integrity (GOI), negative bias temperature instability (NBTI), positive bias temperature instability (BTI), and gate oxide hot carrier injection (HCI). Therefore, it would be advantageous to provide a circuit and method capable of repeatedly monitoring the SNM of SRAM cells in order to, for example, allow preemptive actions to be taken to prevent stability fails.